Circuit designs implemented within integrated circuit devices (ICs) are routinely tested for functionality. It is common practice to simulate circuit designs for ICs using any of a variety of different Electronic Design Automation (EDA) tools. Typically, such circuit designs are to be used within a larger system. For example, the IC usually is mounted upon a circuit board with one or more other ICs and various other electronic components. It then becomes necessary to ensure that each IC interacts with each other IC, on the circuit board level, appropriately.
As I/O switching frequencies have increased and voltage levels have decreased, accurate analog simulation of I/Os has become an essential part of modern high-speed digital system design. By accurately simulating the I/O buffers, termination, and circuit board traces, designers can significantly shorten their time-to-market of new designs. By identifying signal integrity related issues at the beginning of the design cycle, the number of board and/or IC fixes is decreased.
Traditionally SPICE analysis has been used extensively in areas like IC design, where a high level of accuracy is required. However, in the printed circuit board (PCB) and systems domain, there are several disadvantages to the SPICE method, both for the user and the device vendor. Since SPICE simulations model a circuit at transistor level, it is necessary for the SPICE models to contain detailed information about the circuit and process parameters. For most IC vendors, this type of information is regarded as proprietary and there is usually a great deal of resistance against making the models public.
Although SPICE simulation accuracy is typically very good, a significant limitation with any simulation method is simulation speed. Simulation speeds are particularly slow for transient simulation analysis, which is most often used when evaluating signal integrity performance. SPICE simulation has a further disadvantage in that not all SPICE simulators are fully compatible. Oftentimes, default simulator options are not the same in different SPICE simulators. As there are some very powerful options that control accuracy, convergence, and the algorithm type, any options that are not consistent may give rise to poor correlation in simulation results across different simulators. In addition, because of the different variants of SPICE, these models are often incompatible between simulators. Thus, models must be extracted for a specific simulator. An alternative to SPICE simulation is the use of an Input/Output model (I/O model) for simulation.
I/O models express the I/O behavior of individual pins of an IC according to an I/O model standard and can be used to simulate I/O interaction between ICs and other circuits. One widely used I/O model standard is IBIS (I/O Buffer Information Specification). IBIS allows access to accurate I/O buffer models while protecting intellectual property. The IBIS specification is maintained by the EIA/IBIS Open Forum, which has members from a large number of IC and EDA vendors. Other I/O models include IBIS-AMI, VHDL-AMS, Verilog-A, and I/O modeling within SPICE.
The core of the IBIS model consists of a table of current versus voltage and timing information. This is very attractive to the IC vendor as the I/O internal circuit is treated as a black box. This way, transistor level information about the circuit and process details is not revealed.
Models that specify the behavior of I/O pins for the IC can be created that conform to IBIS or another available I/O specification. Using I/O models has a great advantage to the user in that simulation speed is significantly increased over full SPICE simulation, while accuracy is only slightly decreased. I/O pin models that are created for the I/O pins of an IC can be used to implement transmission line-like simulation of the various signals exchanged between I/O pins of the ICs on a circuit board.
Currently I/O models are generated from completed circuit designs. This process creates a bottleneck in the development cycle, because other components or circuit boards which interact with the circuit design cannot be simulated to verify I/O behavior until the I/O model is generated. The present invention may address one or more of these issues.